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HA456
Data Sheet August 14, 2006 FN4153.5
120MHz, Low Power, 8x8 Video Crosspoint Switch
The HA456 is the first 8 x 8 video crosspoint switch suitable for high performance video systems. Its high level of integration significantly reduces component count, board space, and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight video input signals to any, or all, matrix outputs. Each matrix output connects to an internal, high-speed (200V/s), unity gain buffer capable of driving 400 and 5pF to 2V. For applications requiring gain or increased drive capability, the HA456 outputs can be connected directly to two HFA1412 quad, gain of two video buffers, which are capable of driving 75 loads. This crosspoint's true high impedance three-state output capability, makes it feasible to parallel multiple HA456s and form larger switch matrices.
Features
* Fully Buffered Inputs and Outputs (AV = +1) * Routes Any Input Channel to Any Output Channel * Switches Standard and High Resolution Video Signals * Serial or Parallel Digital Interface * Expandable for Larger Switch Matrices * Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 120MHz * High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 200V/s * Differential Gain and Phase . . . . . . . . . . . . . .0.05%, 0.05 * Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . . -55dB * Pb-Free plus anneal available (RoHS compliant)
Applications
* Professional Video Switching and Routing * Security and Video Editing Systems
Ordering Information
PART NUMBER HA456CM PART MARKING HA456CM TEMP. RANGE (C) 0 to 70 0 to 70 PACKAGE 44 Ld PLCC 44 Ld PLCC (Pb-free) PKG. DWG. # N44.65 N44.65
Pinout
HA456 (PLCC) TOP VIEW
IN0 A1 A2 D0/SER IN D1/SER OUT NC V+ OUT0 D2 OUT1 D3
6 54 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28
HA456CMZ HA456CMZ (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
A0 IN1 NC IN2 DGND NC IN3 DGND IN4 EDGE/LEVEL IN5
7 8 9 10 11 12 13 14 15 16 17
OUT2 VOUT3 AGND OUT4 NC AGND OUT5 AGND OUT6 V+
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
SER/PAR IN7 VNC WR LATCH CE CE OUT7
V+ IN6
HA456 HA456 Functional Block Diagram
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7
OUTPUT BUFFERS (AV = 1)
OUT0 EN0
HA456 8x8 SWITCH MATRIX
OUT7 EN7 EN0:7
LATCH SLAVE REGISTER EDGE/LEVEL
SER/PAR MASTER REGISTER D0/SER IN
WR CE CE D1/SER OUT
A0
A1
A2
D2
D3
2
FN4153.5 August 14, 2006
HA456 Pin Descriptions
NAME NC D1/ SER OUT No connect. Not internally connected. Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift register) for cascading multiple HA456s in serial programming mode. Simply connect Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy chain multiple devices. Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift register) for serial programming mode. Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode. Analog Video Input Lines. Digital Ground. Connect both DGND pins to AGND. A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin strapped high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on the WR rising edge (not recommended for serial mode operation). Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND (Figure 2). A user strapped input that defines whether the serial (SER/PAR = 1) or parallel (SER/PAR = 0) digital programming interface is being utilized. Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND (Figure 2). WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (if D3:0 = 0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111), on the WR rising edge (see Table 1). Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software "Latch" (see Table 1). Chip Enable. When CE = 0 and CE = 1, the WR line is enabled. Chip Enable. When CE = 0 and CE = 1, the WR line is enabled. Analog Video Outputs. Analog Ground. Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming. Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming. FUNCTION
D0/SER IN A2, A1, A0 IN0-IN7 DGND EDGE/LEVEL
V+ SER/PAR VWR
LATCH
CE CE OUT7-OUT0 AGND D3 D2
3
FN4153.5 August 14, 2006
HA456
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V Negative Supply Voltage (V-) Referred to AGND. . . . . . . . . . . . -6V DGND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND 1V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSUPPLY Digital Input Voltage . . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V) ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . . 1.5kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Moisture Sensitivity (see Technical Brief TB363) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VSUPPLY = 5V, AGND = DGND = 0V, RL = 400 (Note 2), Unless Otherwise Specified. (NOTE 3) TEST LEVEL A A A A TEMP (C) 25 Full 25 Full 25 Full 25 Full Full Full 25 25 25 25
PARAMETER Voltage Gain
TEST CONDITIONS VIN = -1.5V to +1.5V, Worst Case Switch Configuration
MIN 0.992 0.99 2 -
TYP 0.996 0.995 0.001 0.001 68 71 47 47 2.5 1.6 0.15 22 4 3.2
MAX 1.00 1.00 0.004 0.005 80 83 65 67 12 -
UNITS V/V
Channel-to-Channel Gain Mismatch
V/V
Supply Current
All Outputs Enabled, RL = Open, VIN = 0V, Total for All V+ (3) or V- (2) Pins All Outputs Disabled, RL = Open, Total for All V+ (3) or V- (2) Pins
A A A A A
mA
Disabled Supply Current
mA
Input Voltage Range Analog Input Current Input Noise (RS = 75) VIN = 0V DC to 40MHz 10kHz Analog Input Resistance Analog Input Capacitance (Input Connected to One Output or All Outputs, Note 6) Output Offset Voltage VIN = 0V, Worst Case Switch Configuration DC
V A mVRMS nV/Hz M pF
A B B C B
A A A A B
25 Full 25 Full Full 25 Full 25 25 Full
-18 -20 2.2 2.1 -
-6.5 -7.5 2 4 20 2.48 2.47 0.25 0.2 1
5 6 11 13 5 10
mV
Channel-to-Channel Offset Voltage Mismatch Offset Voltage Drift Output Voltage Swing VIN = 2.5V
mV
V/C V V A A
A A
Output Resistance Output Leakage Current (Including D1/SER OUT)
Enabled, DC All Outputs Disabled, VOUT = 2.5V
B A A
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FN4153.5 August 14, 2006
HA456
Electrical Specifications
VSUPPLY = 5V, AGND = DGND = 0V, RL = 400 (Note 2), Unless Otherwise Specified. (Continued) (NOTE 3) TEST LEVEL A B DC, VS = 4.5V to 5.5V, VIN = 0V VIN = 0V or 5V A A A A A SER OUT Logic Low Voltage SER OUT Logic High Voltage AC CHARACTERISTICS (Note 4) -3dB Bandwidth (Note 6) CL = 5pF, VIN = 200mVP-P CL = 5pF, VIN = 1VP-P CL = 5pF, VIN = 2VP-P Slew Rate (Note 6) All Hostile Crosstalk (Note 6) All Hostile Off Isolation (Note 6) Differential Phase VOUT = 4VP-P 10MHz, VIN = 1VP-P, RL =1k 10MHz, VIN = 1VP-P NTSC or PAL, RL = 1k NTSC or PAL, RL 10k Differential Gain NTSC or PAL, RL = 1k NTSC or PAL, RL 10k TIMING CHARACTERISTICS (See Figure 3 for More Information) Write Pulse Width High (tWH) Write Pulse Width Low (tWL) Chip-Enable Setup Time to Write (tCS) Chip-Enable Hold Time From Write (tCH) Data and Address Setup Time to Write (tDS) Parallel Mode Serial Mode Data and Address Hold Time From Write (tDH) Latch Pulse Width (tL) Latch Delay From Write (tD) LATCH Edge to Output Disabled (tOFF) LATCH Edge to Output Enabled (tON) Output Break-Before-Make Delay (tON - tOFF) NOTES: 2. For the lowest crosstalk, and the best composite video performance, use RL 1k. 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. See AC Test Circuits (Figure 6 through Figure 9). 5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit. 6. See Typical Performance Curves for more information. Serial Mode Serial Mode Serial Mode A A A A A A A A A B B B Full Full Full Full Full Full Full Full Full Full Full Full 20 20 5 5 20 20 25 40 40 30 185 155 ns ns ns ns ns ns ns ns ns ns ns ns B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 120 70 50 200 -55 70 0.05 0.05 0.05 0.02 MHz MHz MHz V/s dB dB % % Serial Mode, IOL = 1.6mA Serial Mode, IOH = -0.4mA A A TEMP (C) 25 25 Full Full Full 25 Full Full Full
PARAMETER Output Resistance Output Capacitance (Output Disabled) Power Supply Rejection Ratio Digital Input Current (Note 5) Digital Input Low Voltage Digital Input High Voltage
TEST CONDITIONS Output Disabled
MIN 0.6 45 2.0 2.2 3.0
TYP 15 3.5 53 -
MAX 1 0.8 0.4 -
UNITS M pF dB A V V V V V
5
FN4153.5 August 14, 2006
HA456 Application Information
HA456 Architecture
The HA456 video crosspoint switch consists of 64 switches in an 8 x 8 grid (Figure 1). Each input is fully buffered and presents a constant input capacitance whether the input connects to one output or all eight outputs. This yields consistent input termination impedances regardless of the switch configuration. The 8 matrix outputs are followed by 8 unity gain, wideband, tristatable buffers optimized for driving 400 and 5pF loads. The output disable function is useful for multiplexing two or more HA456s to create a larger input matrix (e.g., two multiplexed HA456s yield a 16x8 crosspoint). The HA456 outputs can be disabled individually or collectively under software control. When disabled, an output enters a high-impedance state. In multichip parallel applications, the disable function prevents inactive outputs from loading lines driven by other devices. Disabling an unused output also reduces power consumption. The HA456 outputs connect easily to two HFA1412 quad, gain-of-two buffers when 75 loads must be driven. EDGE/LEVEL=1. Otherwise, the Slave Register updates asynchronously (while LATCH=0, if EDGE/LEVEL=0). WR is logically AND'ed with CE and CE to allow active high or active low chip enable.
7-Bit Parallel Mode
In the parallel programming mode (SER/PAR = 0), the 7 control bits (A2:0 and D3:0) typically specify an output channel (A2:0) and the corresponding action to be taken (D3:0). Command codes are available to enable or disable all outputs, or individual outputs, as shown in Table 1. Each output has 4-bit Master and Slave Registers associated with it, that hold the output's currently selected input address (defined by D3:0). The input address - if applicable - is loaded into the Master Register on the rising edge of WR. If the HA456 is in level mode, and if LATCH =0 (asynchronous switching), then the input address flows through the transparent Slave Register, and the output immediately switches to the new input. For synchronous switching on the rising edge of LATCH, strap the HA456 for edge mode, program all the desired switch connections, and then drive an inverted pulse on the LATCH input. Note: Operations defined by commands 1011 - 1111 occur asynchronously on the WR rising edge, without regard for the state of LATCH or EDGE/LEVEL.
Power-On RESET
The HA456 has an internal power-on reset (POR) circuit that disables all outputs at power-up, and presets the switch matrix so that all outputs connect to IN0. In parallel mode, the desired switch state may be programmed before the outputs are enabled. In serial mode, all outputs are connected to GND each time they are enabled, so switch state programming must occur after the output is enabled.
32-Bit Serial Mode
In the serial programming mode, all master registers are loaded with data, making it unnecessary to specify an output address (A2:0). The input data format is D3-D0, starting with OUT0 and ending with OUT7 for 32 total bits (i.e., first bit shifted in is D3 for OUT0, and 32nd bit shifted in is D0 for OUT7). Only codes 0000 through 1010 are valid serial mode commands. Code 1010 disables an individual output, while code 1001 enables it. After data is shifted into the 32-bit Master Register, it transfers to the Slave Register on the rising edge of the LATCH line (Edge mode), or when LATCH=0 (Level mode, see Figure 5).
AV = +2
Digital Interface
The desired switch state can be loaded using a 7-bit parallel interface mode or 32-bit serial interface mode (see Tables 1 through 3). All actions associated with the WR line occur on its rising edge. The same is true for the LATCH line if
HA456
75
VIDEO OUT 75
VIDEO INPUTS
INPUT BUFFERS
WR LATCH
8X8 SWITCH MATRIX
HFA1412 OR HFA1405
OUTPUT SELECT
A2 A1 A0 D3 D2 D1/SER OUT D0/SER IN
INPUT SELECT AND COMMAND CODES OR SERIAL I/O
AV = +2
FIGURE 1. TYPICAL CABLE DRIVING APPLICATION
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FN4153.5 August 14, 2006
HA456
TABLE 1. PARALLEL INTERFACE COMMANDS A2:0 Selects Output Being Programmed D3:0 0000 to 0111 1000 1011 1100 Address Inputs are Irrelevant for These Functions 1101 1110 1111 1001 or 1010 ACTION Connect the input defined by D3:0 to the output selected by A2:0. Doesn't enable a disabled output. Connect the output selected by A2:0 to GND. Doesn't enable a disabled output. Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged. Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged. Asynchronously disable all outputs, and leave the Master Register unchanged. Asynchronously enable all outputs, and leave the Master Register unchanged. Send a Software "Latch" pulse to the Slave Register to load it from the Master Register, iff, the LATCH input=1. If the LATCH input=0, then this command is a NOP. The Master Register is unchanged by this command. Do not use these codes in the parallel programming mode. These codes are for serial programming only. TABLE 2. SERIAL INTERFACE COMMANDS D3:0 0000 to 0111 1000 1001 1010 1011 to 1111 ACTION Connect the output to the input channel defined by D3:0. Doesn't enable a disabled output. Connect the output to GND. Doesn't enable a disabled output. Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable outputs after power is applied, but before programming the switch configuration. Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after re enabling the output. Do not use these codes in the serial programming mode. TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS SER/PAR H L L D3 X H L D2 X Parallel Data Input Parallel Data Input D1 Serial Data Output Parallel Data Input Parallel Data Input D0 Serial Data Input Parallel Data Input Parallel Data Input A2:0 X Output Address Output Address COMMENT 32-Bit Serial Mode Parallel Mode; D2:0 define the command to be executed Parallel Mode; D2:0 define the Input Channel
Figure 2 shows a typical application of the HA456 with HFA1412 quad, gain-of-two buffers at the outputs to drive 75 loads. This application shows the HA456 digital-switch control interface set up in the 7-bit parallel mode. The HA456 uses 7 data lines and 3 control lines (WR, CE and LATCH). The input/output information is presented to the chip at A2:0 and D3:0 by a parallel printer port. The data is stored in the Master Registers on the rising edge of WR. When the LATCH line goes high, the switch configuration loads into the Slave Registers, and all 8 outputs reconfigure at the same time. Each 7-bit word updates only one output at a time.
If several outputs are to be updated, the data is individually loaded into the Master Registers. Then, a single LATCH pulse can reconfigure all channels simultaneously. An IBM compatible PC loads the programming data into the HA456 via its parallel port (LPT1) using a simple BASIC program.
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FN4153.5 August 14, 2006
HA456
HFA1412 (AV = +2) HA456 6 8 10 13 15 17 14 21 OUT0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 CE EDGE/LEVEL 19 1 2 3 4 5 6 7 8 14 16 18 NC 24 WR V+ 3 2 42 40 7 5 4 AGND D0/SER IN D1/SER OUT DGND D2 VD3 A0 A1 SER/PAR A2 CE 25 LATCH 43 41 34 37 35 32 30 28 27 16 RS RS 3 IN 1 5 IN 2 10 IN 3 12 IN 4 V+ 4 OUT1 1 7 OUT2 8 OUT3 14 OUT4 -IN0:3 2, 6 9, 13 V11 -5V 75 VOUT 75
VIDEO INPUTS
RS
18, 29, 44 31, 33, 36 11, 14 22, 38
+5V
-5V
30 33 36
20 26
NOTE: All decoupling capacitors 0.1F Ceramic (1 per supply pin). For lowest crosstalk connect unused pins to GND use RS to tune the overall output response. FIGURE 2. TYPICAL HIGH PERFORMANCE, PARALLEL MODE APPLICATION CIRCUIT (SEE FIGURE 18)
Waveforms
A2:0, D3:0
VALID DATA
VALID DATA
tDS tCS CE
tDH
tCH
tWL WR tD tWH
LATCH (EDGE MODE)
tL
FIGURE 3. DIGITAL TIMING REQUIREMENTS
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FN4153.5 August 14, 2006
HA456 Waveforms
(Continued)
DATA (N) DATA (N + 1) DATA (N + 2)
WR LATCH
MASTER REGISTER CONTENTS
DATA (N)
DATA (N + 1)
DATA (N + 2)
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 0)
DATA (N)
DATA (N + 1)
DATA (N + 2)
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 1)
DATA (N)
DATA (N + 1)
DATA (N + 2)
FIGURE 4. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)
NEW DATA FOR OUT0
NEW DATA FOR OUT1 TO OUT6
NEW DATA FOR OUT7
SER IN
D3 1st WRITE
D2
D1
D0
D3
D2
D3
D2
D1
D0 32nd WRITE
WR
LATCH t=0 SLAVE REGISTER CONTENTS (EDGE/LEVEL = 0)
OLD DATA
NEW DATA
SLAVE REGISTER CONTENTS (EDGE/LEVEL = 1)
OLD DATA
NEW DATA
FIGURE 5. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)
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FN4153.5 August 14, 2006
HA456 AC Test Circuits
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VOUT IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT
VIN = 1VP-P, SWEEP FREQUENCY
VIN = 1VP-P, AT 10MHz
FIGURE 6. -3dB BANDWIDTH (NOTES 7-10)
FIGURE 7. ALL HOSTILE OFF ISOLATION (NOTES 10-12)
IN0 IN1 IN2 IN3 7 X 75 IN4 IN5 IN6 IN7
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VOUT VOUT VOUT VOUT VOUT VOUT VOUT 75
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VOUT
VIN = 1VP-P, AT10MHz
VIN = 1VP-P, AT 10MHz
FIGURE 8. SINGLE CHANNEL CROSSTALK (NOTES 10, 13-16) NOTES: 7. Program the desired input to output combination (e.g., IN7 to OUT1). 8. Enable the selected output(s).
FIGURE 9. ALL HOSTILE CROSSTALK (NOTES 10, 15, 17-19)
9. Drive the selected input with VIN, and measure the -3dB frequency at the selected output (VOUT). 10. Load all outputs with the desired RL. 11. Disable all outputs. 12. Drive all inputs with VIN and measure VOUT at any output; isolation (in dB) = -20log10 (VOUT/VIN). 13. Drive VIN on one input which connects to one output (e.g., IN7 to OUT7). 14. Terminate all other inputs to GND. 15. Enable all outputs. 16. Measure VOUT at any undriven output; crosstalk (in dB) = 20log10 (VOUT/VIN). 17. Terminate one input to GND, and connect that input to a single output (e.g., IN0 to OUT0). 18. Drive the other seven inputs with VIN, and connect these active inputs to the remaining seven outputs. 19. Measure VOUT at the quiescent output; crosstalk (in dB) = 20log10 (VOUT/VIN).
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FN4153.5 August 14, 2006
HA456 Typical Performance Curves
1.4 1.2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TIME (20ns/DIV.) 1.0 0.8 0.6 0.4 0.2 0 -0.2
VSUPPLY = 5V, TA = 25C, RL = 400, Unless Otherwise Specified
4.0 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -4.0 TIME (20ns/DIV.)
FIGURE 10. SMALL SIGNAL PULSE RESPONSE
FIGURE 11. LARGE SIGNAL PULSE RESPONSE
3 GAIN (dB) GAIN 0 -3 -6 PHASE VOUT = 1VP-P
VOUT = 0.2VP-P
1.0 GAIN (dB) VOUT = 2VP-P 0 PHASE () 45 90 VOUT = 1VP-P VOUT = 0.2VP-P VOUT = 2VP-P 135 180 200M 0.5 0 -0.5 -1.0 -1.5 VOUT = 0.2VP-P -2.0 1M 10M FREQUENCY (Hz) 10M 200M VOUT = 1VP-P
1M
10M FREQUENCY (Hz)
10M
FIGURE 12. FREQUENCY RESPONSE
FIGURE 13. GAIN FLATNESS
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
VIN = 1VP-P
20 30 40 OFF ISOLATION (dB) RL = 150 RL = 1k 50 60 70 80 90 100 110
VIN = 1VP-P RL = 1k
CROSSTALK (dB)
RL = 150
1M
10M FREQUENCY (Hz)
100M
200M
1M
10M FREQUENCY (Hz)
100M
200M
FIGURE 14. ALL HOSTILE CROSSTALK
FIGURE 15. ALL HOSTILE OFF-ISOLATION
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FN4153.5 August 14, 2006
HA456 Typical Performance Curves
250 225 SLEW RATE (V/s) 200 175 150 125 100 75 50 0.5 1.0 1.5 2.0 2.5 3.5 4.0 VOUT (VP-P) 3.0 4.5 5.0 5.5 6.0 0.03M 0.1M 1M FREQUENCY (Hz) 10M MAGNITUDE (dB)
VSUPPLY = 5V, TA = 25C, RL = 400, Unless Otherwise Specified (Continued)
120 110 1 INPUT TO ALL OUTPUTS 100 90 80 70 60 PHASE 0 10 20 30 100M PHASE () 1 INPUT TO 1 OUTPUT
FIGURE 16. SLEW RATE vs VOUT
FIGURE 17. INPUT IMPEDANCE vs FREQUENCY
RL =150 RS = 0
3 GAIN (dB) 0 -3 -6
VOUT = 0.5VP-P
VOUT = 1VP-P
1M
10M FREQUENCY (Hz)
100M
200M
FIGURE 18. FREQUENCY RESPONSE OF HA456-HFA1412 COMBINATION (PER FIGURE 2)
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FN4153.5 August 14, 2006
HA456 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C
N44.65 (JEDEC MS-018AC ISSUE A)
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 0.685 0.650 0.291 0.685 0.650 0.291 44 MAX 0.180 0.120 0.695 0.656 0.319 0.695 0.656 0.319 MILLIMETERS MIN 4.20 2.29 17.40 16.51 7.40 17.40 16.51 7.40 44 MAX 4.57 3.04 17.65 16.66 8.10 17.65 16.66 8.10 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
A1 D D1 D2 E E1
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
E2 N
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN VIEW "A" TYP.
0.025 (0.64) MIN
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN4153.5 August 14, 2006

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